A piecewise Transistor-Level Simulation Technique for the Steady State and Phase Noise Analysis of Integer N PLLs

Abstract : Print Request Permissions Save to Project Brute force transistor-level simulation of PLL is precise but suffers long simulation time and convergence problems, both with time domain and harmonic-balance techniques. On the other hand common behavioral phase domain simulation is rapid but does not consider the non-idealities at transistor-level. In this paper we propose a piecewise transistor-level simulation method, which stands between the two above approaches, and combines the advantages of both. In the proposed method, a hierarchical simulation process is applied to compute an accurate steady state, and a small-signal model is created for phase noise calculation. The phase noise is obtained rapidly and accurately.
Type de document :
Communication dans un congrès
Liste complète des métadonnées

https://hal-unilim.archives-ouvertes.fr/hal-00924808
Contributeur : Edouard Ngoya <>
Soumis le : mardi 7 janvier 2014 - 11:01:49
Dernière modification le : jeudi 11 janvier 2018 - 06:17:28

Identifiants

  • HAL Id : hal-00924808, version 1

Collections

Citation

Bo Wang, Edouard Ngoya. A piecewise Transistor-Level Simulation Technique for the Steady State and Phase Noise Analysis of Integer N PLLs. Microwave Symposium, 2008 IEEE MTT-S International, Jun 2008, Atlanta, United States. pp.1429 - 1432. ⟨hal-00924808⟩

Partager

Métriques

Consultations de la notice

66